The present invention relates to SRAM devices and, more particularly, to a 2-port SRAM device (dual-port SRAM device).
Each of Japanese Laid-Open Patent Publications Nos. 10-178110 and 9-270468 discloses the layout of a memory cell composed of six transistors in an SRAM device. In particular, each of the foregoing publications discloses a method for reducing the aspect ratio (which is the ratio of the width of the memory cell in the direction in which a word line extends to the width thereof in the direction in which a bit line extends in the present specification) of the memory cell composed of six transistors shown in FIG. 7A, i.e., a method for laying out the cell such that the width thereof in the direction in which the word line extends is larger than the width thereof in the direction in which the bit line extends. Specifically, each of the publications discloses the layout in which P-wells 102a and 102b are placed on both sides of an N-well 101 to have the N-well 101 interposed therebetween, as shown in FIG. 7B. In the layout, the six transistors (MN0, MN1, MN2, MN3, MPO, and MP1) are arranged in generally symmetrical relation relative to the center point of the memory cell.
In the layout of a memory cell 100 shown in FIG. 7A and FIG. 7B, bit lines BL and /BL are disposed on the P-wells 102a and 102b, respectively. The drive transistors MN0 and MN1 each formed of an NMOS are laid out in generally symmetrical relation relative to the center point of the memory cell, as described above, and disposed on the P-wells 102a and 102b, respectively. Likewise, the access transistors MN2 and MN3 each formed of an NMOS are also laid out in generally symmetrical relation relative to the center point P100 of the memory cell and disposed on the P-wells 102a and 102b, respectively. The load transistors MP0 and MP1 each composed of a PMOS are also laid out in generally symmetrical relation relative to the center point P100 of the memory cell and disposed on the N-well 101. The load transistors MP0 and MP1 are arranged in two rows parallel to each other and in a direction in which the bit lines extend so that a PMOS region corresponding thereto has a large width (width of the N-well 101).
A description will be given herein below to the case of laying out a memory cell in a 2-port 8-transistor SRAM device shown in FIG. 8A by using the method disclosed in the foregoing publications. FIG. 8B shows a memory cell 200 in the 2-port 8-transistor SRAM device that has been laid out by using the technology disclosed in the foregoing publications. FIG. 9 diagrammatically shows a structure of the bit lines and word lines of the memory cell 200 shown in FIG. 8B. As indicated by the broken lines, the region shown in FIG. 8B and FIG. 9 corresponds to two memory cells (2 bits). The region defined by the broken lines in FIG. 9 is a memory cell region 200xe2x80x2 corresponding to the memory cell 200 shown in FIG. 8B.
As shown in FIG. 8B and FIG. 9, the prior art technology positions P-wells 202a and 202b on both sides of an N-well 201 such that the N-well 201 is interposed therebetween. For the sake of convenience, two ports will be hereinafter referred to as ports A and B. A pair of bit lines (BLa, /BLa) for the port A are disposed on the P-wells 202a and 202b, respectively. A pair of bit lines (BLb, /BLb) for the port B are also disposed on the P-wells 202a and 202b, respectively. Consequently, the eight transistors are arranged in generally symmetrical relation relative to the center point P200 of the memory cell 200.
The pair of access transistors (MN4, MN5) for the port A are disposed on the P-wells 202a and 202b, respectively. The pair of access transistors (MN2, MN3) for the port B are also disposed on the P-wells 202a and 202b, respectively. The load transistors (MP0, MP1) each formed of a PMOS are arranged in two rows, similarly to the foregoing memory cell 100, to be laid out in generally symmetrical relation relative to the center point P200 of the memory cell 200 and disposed on the N-well 201. The load transistors MP0 and MP1 are arranged in two rows parallel to each other and in the direction in which the bit lines extend such that a PMOS region has a large width (width of the N-well 201).
The ports A and B are normally required to operate completely asynchronously. In the layout of the memory cell 200 shown in FIG. 8B, the bit lines BLa and BLb are disposed adjacent to the P-well 202a and the bit lines /BLa and /BLb are disposed adjacent to the P-well 202b. If the bit lines (BLa, /BLa) for the port A have a read potential difference of several tens of millivolts held therebetween and respective potentials on the bit lines (BLb, /BLb) for the port B vary dynamically to have a write potential difference of 1000 mV or more therebetween, wire-to-wire coupling occurs between the bit lines BLa and BLb disposed adjacent to each other and between the bit lines /BLa and /BLb disposed adjacent to each other. This significantly changes the read potential difference of several tens of millivolts between the bit lines (BLa, /BLa) for the port A and may destroy stored data.
The present invention has been achieved to solve the foregoing problem and it is therefore an object of the present invention to provide a highly reliable SRAM device.
An SRAM device according to the present invention comprises a memory cell, the memory cell including: a first pair of bit lines connected to a first port; a second pair of bit lines connected to a second port: a first inverter; and a second inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an input terminal of the first inverter, the memory cell having a first region in which an impurity of a first conductivity type is diffused and second and third regions each of a second conductivity type, the second and third regions being adjacent to the first region and opposed to each other with the first region interposed therebetween, the first pair of bit lines being disposed on the second region and the second pair of bit lines being disposed on the third region.
According to the present invention, even if the first and second ports operate completely asynchronously, the influence of wire-to-wire coupling is suppressed or prevented since the first and second ports are disposed physically at a distance from each other.
The first inverter may be composed of first and second MIS transistors, the second inverter may be composed of third and fourth MIS transistors, the memory cell may further comprise: a fifth MIS transistor provided between the output terminal of the first inverter and one of the first pair of bit lines; a sixth MIS transistor provided between the output terminal of the first inverter and one of the second pair of bit lines; a seventh MIS transistor provided between the output terminal of the second inverter and the other of the first pair of bit lines; and an eighth MIS transistor provided between the output terminal of the second inverter and the other of the second pair of bit lines, and the first, second, third, fourth, fifth, sixth, seventh, and eighth MIS transistors may have respective channels oriented in approximately the same direction.
Preferably, the second and fourth MIS transistors are formed on the first region, the first, fifth, and seventh MIS transistors are formed on the second region, the third, sixth, and eighth MIS transistors are formed on the third region, the first and third MIS transistors are disposed in generally symmetrical relation relative to a center point of the memory cell; the fifth and sixth MIS transistor are disposed in generally symmetrical relation relative to the center point of the memory cell, the seventh and eighth MIS transistor are disposed in generally symmetrical relation relative to the center point of the memory cell, and the second and fourth MIS transistor are disposed in generally symmetrical relation relative to the center point of the memory cell.
In the arrangement, the memory cell has a highly symmetrical structure. This achieves the prominent effects of providing an electrical characteristic with a higher degree of symmetry than has been provided conventionally and providing an SRAM device operating with higher stability. Since the memory cell has a highly symmetrical structure, even if slight misalignment occurs in a lithographic step of the fabrication process or the like, the misalignment itself has symmetry. This suppresses a problem associated with the electric characteristic resulting from the misalignment and improves the production yield of the SRAM device.
The SRAM device further comprises: a first gate wire providing connections among a gate of the fifth MIS transistor, a gate of the seventh MIS transistor, and the first port; and a second gate wire providing connections among a gate of the sixth MIS transistor, a gate of the eighth MIS transistor, and the second port wherein the first and second gate wires are disposed in generally symmetrical relation relative to the center point of the memory cell.
In accordance with the present invention, each of the fifth and seventh MIS transistors connected to the first port is placed on the second region. On the other hand, each of the sixth and eighth MIS transistors connected to the second port is placed on the third region. Consequently, the first and second gate wires connected to the first and second ports, respectively, are connected to the respective gate electrodes of the MIS transistors and do not intersect each other. This allows the first and second gate wires to be disposed in generally symmetrical relation relative to the center point of the memory cell and thereby reduces the degree of asymmetry of the electric characteristic of the memory cell.
Preferably, the second and fourth MIS transistors have respective channels oriented in parallel to a direction in which the first pair of bit lines extend and disposed on a straight line passing through the center point of the memory cell.
The arrangement allows a reduction in the width of the first region and provides a memory cell with a high degree of integration.
The first conductivity type may be an n-type and the second conductivity type may be a p-type.
Preferably, the SRAM device further comprises: a first active region provided with the first MIS transistor and either one of the fifth and seventh MIS transistors and indiscrete in the direction in which the bit lines extend; and a second active region provided with the third MIS transistor and either one of the sixth and eighth MIS transistors and indiscrete in the direction in which the bit lines extend.
In the arrangement, the first MIS transistor and either one of the fifth and seventh MIS transistors, each provided on the first active region, and the third MIS transistor and either one of the sixth and eighth MIS transistors, each provided on the second active region, are disposed in generally symmetrical relation relative to the center point of the memory cell. Since the first and second active regions are disposed in generally symmetrical relation relative to the center point of the memory cell, an electrically symmetrical characteristic is achievable. Since each of the first and second active regions is indiscrete in the direction in which the bit lines extend, contacts for providing a connection between contact nodes are no more necessary.
Preferably, the first active region has a first expanded portion, the second active region has a second expanded portion, the first MIS transistor is formed on the first expanded portion, and the third MIS transistor is formed on the second expanded portion.
In the arrangement, the first and second expanded portions are formed in generally symmetrical relation relative to the center point of the memory cell. Accordingly, an electrically symmetrical characteristic is achievable, while a high degree of integration is retained.
The first and second expanded portions may be formed on the respective parts of the first and second active regions each opposed to the first region.
The first and second expanded portions may be formed on the respective parts of the first and second active regions each opposite to the first region.
Preferably, dummy active regions for increasing respective parasitic capacitances of the first and second inverters are disposed between the first region and the first active region and between the first region and the second active region.
The arrangement increases the capacity of the data storage section of the memory cell and suppresses or prevents the destruction of data (soft error) caused by momentary dissipation of charge from the data storage section under the radiation of a radio-active ray.
Preferably, the SRAM device further comprises: a power supply line disposed between the first and second pairs of bit lines in parallel relation to the first and second pairs of bit lines; a first ground line disposed in opposing relation to the power supply line with the first pair of bit lines interposed between the first ground line and the power supply line; and a second ground line disposed in opposing relation to the power supply line with the second pair of bit lines interposed between the second ground line and the power supply line.
In the arrangement, the first pair of bit lines and the second pair of bit lines are interposed between the power supply line and the ground lines. As a result, the first pair of bit lines and the second pair of bit lines are shielded from potential variations and effects mutually exerted thereon are reduced. This positively suppresses or prevents wire-to-wire coupling.